1. Field of the Invention
The present invention relates to a test pattern generation device for a digital circuit.
2. Description of the Prior Art
ASIC semiconductors with a circuit construction which makes it possible to monitor the state of all circuit elements have become the preferred type of test pattern generation device. Testing by a semiconductor with this type of construction detects circuit shorts and breaks and other types of semiconductor defects by switching the state of circuit elements ON and OFF and measuring the result according to the test sequence.
A conventional logic element is described, for example, in Design automation reference 49-12, research seminar, Information Processing Society of Japan. According to the prior art test pattern generation devices, the test patterns are generated by the simulation operation using the real number instead of the logic values. The logic values used in the conventional test pattern generation devices are shown in FIG. 8. The logic value is expressed sequentially increasing from logic 0 through logic X to logic 1.
Using a conventional logic value shown in FIG. 8, more information can be obtained about the logic states in the circuit. For example, in the AND gate shown in FIGS. 11a and 11b, the PG,3 outputs of FIGS. 11a and 11b would both be 0 when the inputs are either (0,0) or (0,1). When the logic state is expressed as a continuous value between logic 0 and logic 1, the logic state of the output section will be a value closer to logic 1 with the case of FIG. 11b than with the case of FIG. 11a. By the use of the continuous value instead of the discrete value, information concerning the logic states of the input section can be obtained from the logic state of the output section. Thus, it is possible to know in which direction the output is easily shifted when the input is varied by just investigating the logic state of the output section, and this can be used to facilitate troubleshooting.
However, according to the prior art test pattern generation device that uses the continuous logic value of FIG. 8, it is not possible to express a definite logic state between logic 0 and logic 1 in the input section and the output section because the logic X expressing an unknown value is positioned midway between logic 0 and logic 1.